HYS72D16500GR Datasheet, PDF (22/29 Pages) Infineon Technologies AG – Low Profile DDR SDRAM-Modules

HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
SPD Contents
Table 12 SPD Codes (cont’d)
Byte#
Description
27
Minimum Row Precharge Time 20 ns
28
Minimum Row Act. to Row Act. 15 ns
Delay t_RRD
29
Minimum RAS to CAS Delay t_RCD 20 ns
30
Minimum RAS Pulse Width t_RAS 45 ns/50 ns
31
Module Rank Density (per Rank) 128 MByte/256 Mbyte
32
Addr. and Command Setup Time 0.9 ns/1.1 ns
33
Addr. and Command Hold Time 0.9 ns/1.1 ns
34
Data Input Setup Time
0.5 ns/0.6 ns
35
Data Input Hold Time
0.5 ns/0.6 ns
36 to 40 Superset Information
–
41
Minimum Core Cycle Time t_RC 65 ns/70 ns
42
Min. Auto Refresh Cmd Cycle 75 ns/80 ns
Time t_FRC
43
Maximum Clock Cycle Time t_CK 12 ns
44
Max. DQS-DQ Skew tDQSQ 0.5 ns/0.6 ns
45
X-Factor tQHS
0.75 ns/1.0 ns
46 to 61 Superset Information
–
62
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 - 62
–
64
Manufactures JEDEC ID Codes –
65 to 71 Manufactures
–
72
Module Assembly Location
–
73 to 90 Module Part Number
–
91 to 92 Module Revision Code
–
93 to 94 Module Manufacturing Date –
95 to 98 Module Serial Number
–
99 to 127 –
–
128 to 255 open for Customer use
–
128MB
x72
1rank
-7
HEX.
50
3C
128MB
x72
1rank
-8
HEX.
50
3C
256MB
x72
1rank
-7
HEX.
50
3C
256MB
x72
1rank
-8
HEX.
50
3C
50
50
50
50
2D
32
2D
32
20
20
40
40
90
B0
90
B0
90
B0
90
B0
50
60
50
60
50
60
50
60
00
00
00
00
41
46
41
46
4B
50
4B
50
0C
0C
0C
0C
32
3C
32
3C
75
A0
75
A0
00
00
00
00
00
00
00
00
A7
9C
C0
B5
C1
C1
C1
C1
Infineon Infineon Infineon Infineon
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Data Sheet
22
Rev. 1.2, 2004-06
10292003-DNYO-BD9L