XC167CS-32F Datasheet, PDF (24/90 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC167-32
Derivatives
Functional Description
3
Functional Description
The architecture of the XC167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC167.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC167.
PSRAM
DPRAM
DSRAM
ProgMem
Flash
256 KBytes
OCDS
Debug Support
Osc / PLL RTC WDT
XTAL
Clock Generation
CPU
C166SV2-Core
EBC
XBUS Control
External Bus
Control
Interrupt &PEC
Interrupt Bus
Peripheral Data Bus
ADC
8/10-Bit
16
Channels
GPT
T2
T3
T4
T5
T6
ASC0 ASC1 SSC0
(USART) (USART) (SPI)
BRGen BRGen BRGen
SSC1
(SPI)
BRGen
CC1
T0
T1
CC2
T7
T8
IIC CC6
T12
T13
BRGen
P 20 Port 9 P 7 Port 6
Port 5
Port 4
Port 3
Port 2
PORT1
66
4
8
16
8
15
8
16
Figure 3 Block Diagram
Twin
CAN
AB
PORT0
16
MCB04323_x7.vsd
Data Sheet
22
V1.0, 2005-06