TLE6210G Datasheet, PDF (24/35 Pages) Infineon Technologies AG – ABS System IC

TLE 6210
TLE 6211
Block Description and Electrical Characteristics
The logic expects the time between two clock edges between 3 and 15 clock-cycles. If
this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched
on and the enable output goes low.
An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is
reached a dominant counter reset signal is generated at the output "=15". This pulse is
generated continuously at
t = (15+3) T1 + n * (16*T1)
after the last valid watchdog pulse was detected.
When internal resets and watchdog edges occur at the same time, the internal reset is
dominant.
10ms
1
WD1
0
1
WD2
0
t > 16 *t_CLK
1
EN
0
15* t_CLK + Delay =
15* t_CLK + 3* t_CLK
Delay (3* t_CLK)
wd-controls-en-2
AD 04/02
Figure 7 Missing watchdog signals cause EN low
V1.2 Data Sheet
24
2002-08