TLE6210G Datasheet, PDF (23/35 Pages) Infineon Technologies AG – ABS System IC

TLE 6210
TLE 6211
Block Description and Electrical Characteristics
4.11
Watchdog
To supervise the operation of 2 m-processors watchdog logic for two input signals is
integrated. The logic expects at each WD1 and WD2 rectangular signals with 10 ms high
and 10 ms low time. Deviations from the expected time are counted as errors and
influence the output signals.
A digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms).
The detection ciruit is described in Figure 12.
After power up and 1or 2 valid watchdog edges the WD logic enables the output Drivers.
WD1 ¹
0
1
WD2 ₀
EN ¹
0
12
10ms
3* t_CLK after the 2nd WD-edge (falling edge)
wd-start-up-with Low
AD 04/02
Figure 5
Enable output EN after correct watchdog signals at WD1 and WD2
are present; WD1 and WD2 start with logic Low
WD1 ¹
0
1
WD2 ₀
EN ¹
0
12
10ms
3 * t_CLK after 1st. WD edge
wd-start-up-with High
AD 04/02
Figure 6
Enable output EN after correct watchdog signals at WD1 and WD2
are present; WD1 and WD2 start with logic High
V1.2 Data Sheet
23
2002-08