AUIRFSA8409-7P Datasheet, PDF (2/11 Pages) Infineon Technologies AG – New Ultra Low On-Resistance

AUIRFSA8409-7P
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
R_JC
Junction-to-Case 
–––
R_JA
Junction-to-Ambient (PCB Mount) 
–––
Static Electrical Characteristics @ T_J = 25°C (unless otherwise specified)
0.4
40
°C/W
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V_(BR)DSS
V_(BR)DSS/T_J
R_DS(on)
V_GS(th)
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
I_DSS
Drain-to-Source Leakage Current
40 ––– –––
––– 0.038 –––
––– 0.50 0.69
2.2 3.0 3.9
––– ––– 1.0
––– ––– 150
V V_GS = 0V, I_D = 250µA
V/°C Reference to 25°C, I_D = 2.0mA
m VGS = 10V, ID = 100A 
V V_DS = V_GS, I_D = 250µA
µA
V_DS = 40V, V_GS = 0V
V_DS = 40V, V_GS = 0V, T_J = 125°C
I_GSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
R_G
Internal Gate Resistance
––– ––– 100
––– ––– -100
––– 2.3 –––
nA
V_GS = 20V
V_GS = -20V

Dynamic Electrical Characteristics @ T_J = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Q_g
Q_gs
Q_gd
Q_sync
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q_g - Q_gd)
180 ––– –––
––– 305 460
––– 84 –––
––– 96 –––
––– 209 –––
S V_DS = 10V, I_D = 100A
I_D = 100A
nC
V_DS = 20V
V_GS = 10V 
t_d(on)
Turn-On Delay Time
––– 21 –––
t_r
Rise Time
––– 94 –––
t_d(off)
Turn-Off Delay Time
––– 150 –––
t_f
Fall Time
––– 90 –––
C_iss
Input Capacitance
––– 13975 –––
C_oss
Output Capacitance
––– 2140 –––
C_rss
Reverse Transfer Capacitance
––– 1438 –––
C_oss eff. (ER) Effective Output Capacitance (Energy Related)  ––– 2620 –––
C_oss eff. (TR) Effective Output Capacitance (Time Related) ––– 3306 –––
Diode Characteristics
V_DD = 20V
ns
I_D = 100A
R_G = 2.7
V_GS = 10V 
V_GS = 0V
V_DS = 25V
pF ƒ = 1.0 MHz
V_GS = 0V, V_DS = 0V to 32V 
V_GS = 0V, V_DS = 0V to 32V 
Symbol
Parameter
Min. Typ. Max. Units
Conditions
I_S
Continuous Source Current
(Body Diode)
––– ––– ^523 A
MOSFET symbol
showing the
I_SM
Pulsed Source Current
(Body Diode) 
––– ––– ^1440* A
integral reverse
p-n junction diode.
V_SD
dv/dt
t_rr
Q_rr
I_RRM
Diode Forward Voltage
Peak Diode Recovery 
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
––– 0.8 1.3 V T_J = 25°C, I_S = 100A, V_GS = 0V 
––– 3.1 ––– V/ns T_J = 175°C, I_S = 100A, V_GS = 40V
–––
–––
–––
–––
59
60
96
98
–––
–––
–––
–––
ns
T_J = 25°C
T_J = 125°C
nC
T_J = 25°C
T_J = 125°C
V_R = 34V,
I_F = 100A
di/dt = 100A/µs
––– 2.7 ––– A T_J = 25°C
Notes:
 Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 360A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
 Repetitive rating; pulse width limited by max. junction
temperature.
 Limited by TJmax, starting TJ = 25°C, L = 0.15mH
RG = 50, IAS = 100A, VGS =10V.
 ISD  100A, di/dt  1070A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width  400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss
while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while
VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended
footprint and soldering techniques refer to application note #AN-994.
 R is measured at TJ approximately 90°C.
 Limited by T_Jmax, starting T_J = 25°C, L = 1mH, R_G = 50, I_AS = 53A, V_GS =10V.
* Pulse drain current is limited to 1440A by source bonding technology
2
2016-01-11