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BTF50060-1TEA_11 Datasheet, PDF (18/38 Pages) Infineon Technologies AG – Smart High-Side Power Switch, One Channel
BTF50060-1TEA
Functional Description
Under reverse polarity condition, the output stage can not block a current flow. It will conduct a load current via
the intrinsic body diode. The current through the output stage has to be limited either by the load itself or by
external circuitry, to avoid over heating of the power stage. Power losses in the power stage during reverse polarity
condition can be calculated by Equation (3):
Prev = (–IL(rev)) × (–VSD(rev))
(3)
Additionally, the current into the logic pins has to be limited to the maximum current described in Chapter 4.1 with
an external resistors. Figure 46 shows a typical application. Resistors RINPUT and RSENSE are used to limit the
current in the logic of the device and in the ESD protection stage. The recommended value for RINPUT = RSENSE =
10kΩ. As long as |-VS(rev)| < 16V, the current through the GND pin of the device is blocked by an internal diode.
5.3.5 Protection during Loss of Ground
In case of loss of the module ground or device ground connection (GND pin) the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF (even if the load remains connected to
ground), regardless if the input is driven HIGH or LOW. In case GND recovers the device may need a reset via
the IN pin to return to normal operation.
5.3.6
Protection during Loss of Load or Loss of VS Condition
In case of loss of load with charged primary inductances the maximum supply voltage has to be limited. It is
recommended to use a Z-diode, a varistor (VZa < 40V) or VS clamping power switches with connected loads in
parallel.
In case of loss of a charged inductive load, disturbances on pin OUT may require a reset on IN pin for the device
to regain normal operation.
In case of loss of VS connection with charged inductive loads, a current path with load current capability has to be
provided, to demagnetize the charged inductances. It is recommended to use a diode, a Z-diode or a varistor
(VZb < 16V, VZL + VD < 16V).
For higher clamp voltages currents through all pins have to be limited according to the maximum ratings. Please
see Figure 18 and Figure 19 for details.
VS
VS
VZb
VZa
GND
Figure 18 Loss of VS
OUT
GND
OUT
VD
VZL
L o ssOfV s.e mf
Datasheet
Speed PROFETTM
18
Rev. 1.2, 2011-09-01