BTF50060-1TEA_11 Datasheet, PDF (10/38 Pages) Infineon Technologies AG – Smart High-Side Power Switch, One Channel

BTF50060-1TEA
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 4 Thermal Resistance
Parameter
Thermal Resistance -
Junction to Case
Thermal Resistance -
Junction to Ambient - 2s2p
Symbol
R_thJC1)
Min.
–
R 1)
thJA_2s2p
–
Values
Typ. Max.
1
1.1
Unit Note /
Number
Test Condition
K/W –
P_4.27
22
–
K/W ²⁾
P_4.29
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Figure 6 and Figure 7 are showing the typical thermal impedance of BTF50060-1TEA mounted according to
Jedec JESD51-2,-5,-7 at natural convection on FR4 1s and 2s2p board. The product (chip + package) was
simulated on a 76.4 × 114.3 × 1.5 mm board with 2 inner copper layers (2× 70µm Cu, 2× 35µm Cu). Where
applicable, a thermal via array under the exposed pad contacted the first inner copper layer. The PCB layer
structure is shown in Figure 8. The PCB layout is shown in Figure 9.
V PLQ IRRWSULQW
V PPð
V PPð
VS
VS
'
W ₃ >VHF @
W ₃ >VHF @
Figure 6
Typical Transient Thermal Impedance Figure 7
Z_th(JA) = f(t_P) for different cooling areas
Typical Transient Thermal Impedance
Z_th(JA) = f(t_P) for PWM operation with
duty cycles D = t / t_period on a 2s2p PCB
Datasheet
Speed PROFET^TM
10
Rev. 1.2, 2011-09-01