Q67060-S6136 Datasheet, PDF (15/18 Pages) Infineon Technologies AG – Addendum for PCN-Datasheet 2004-018-A

PCN 2004-018-A: BTS 5440G
Timing diagrams
All channels are symmetric and consequently the diagrams are valid for channel 1 to channel 4.
Figure 1a: Switching a resistive load,
change of load current in on-condition
IN
V_OUT
t _on
I_L
t_slc(IS)
t _off
t _slc(IS)
Load 1
Load 2
I_S,V_S
t_son(IS)
t
The sense signal is not valid during settling time after
turn on or change of load current. tslc(IS) = 300 µs typ.
Figure 1b: V_bb turn on
IN
Vbb
I_L
Figure 1c: Behaviour of sense output:
Sense current (I_S) and sense voltage (V_S)
as function of load current dependent on
the sense resistor.
Shown is V_S and I_S for three different
sense resistors. Curve 1 refers to a low
resistor, curve 2 to a medium-sized
resistor and curve 3 to a big resistor.
Note, that the sense resistor may not falls
short of a minimum value of 500Ω.
V_S
V_ESD
V_fault
I_S
3
2
1
I_L
1
2
3
I_L(lim)
I_L
I_S = I_L / k_ILIS
V_IS = I_S * R_IS; R_IS = 1kΩ nominal
R_IS > 500Ω
I_S,V_S
proper turn on under all conditions
Page 14
2004-Mar-08