PTFB192503EFL Datasheet, PDF (13/15 Pages) Infineon Technologies AG – Thermally-Enhanced High Power RF LDMOS FETs

PTFB192503EL
PTFB192503FL
Package Outline Specifications
Package H-33288-6
4X R1.524
[R.060]
45° X 2.032
[45° X .080]
4X 30°
V
4X 1.143
[.045] (4 PLS)
D
2X 5.080
[.200] (2 PLS)
4.889±.510
V
[.192±.020]
S
9.779
9.398 _[.385]
CL ^[.370]
19.558±.510
[.770±.020]
2X R1.626
[R.064]
E
G
F
CL
2X 12.700
[.500]
2X 22.860
[.900]
27.940
[1.100]
22.352±.200
[.880±.008]
4.039 ^+-.1.22574
[^.159
] ^+.010
-.005
1.575
[.062] (SPH)
1.016
[.040]
CL
34.036
[1.340]
H-33288-6_po_01_10-03-2012
Diagram Notes—unless otherwise specified:
1. Interpret dimensions and tolerances per ASME Y14.5M-1994.
D₂i_.agr_Pa_rm_imN_ao_ryte_ds_i—_mu_en_nl_se_is_os_nsot_ah_re_erw_mis_me_.s_Ap_le_tec_ri_nfie_ad_te: _{dimensions are inches.}
3. Al¹l t^.ole^Inra^ten^rc^pe^res^t±^d0^im.1^e2ⁿ7^si[^o0ⁿ.0^s0^a5ⁿ]^du^tn^ole^les^rs^ans^cp^ee^sc^pifi^ee^rd^Ao^Sth^Me^Erw^Yi¹s⁴e^..^5M-1994.
4.
Pi²n^.s:
3.
D^PArll–^imtod^alr_era^yri_an^dn;^icmG_ees–^n±sgⁱa_0ot_.n1e^s2; S_7ar[e–_.0ms₀o_5mu_].r_uc^Ane^llt;_eeV_srns–^astV_peeD^d_Dc;^iimfE_iee,_dnF^soi–_tohnN_esr._wC^ai.^rsee.inches.
5. Lead thickness: 0.10 + 0.051/–0.025 mm [0.004 + 0.002/–0.001 inch].
6.
4.
Gold
Pins: G = gate, S
plating thickness:
=_0.s₂o₅u_mrce_ic,_roD_n=_[1d₀ra_min_i,_cV_ro=_inV_chD]Dm, E_a,_xF_.
=
N.C.
5. Lead thickness: 0.10 + 0.051/–0.025 mm [.004 +0.002/–0.001 inch].
6. Gold plating thickness: 0.25 micron [10 microinch] max.
Data Sheet
13 of 15
Rev. 09.1, 2016-06-13