ICE3PCS01G Datasheet, PDF (13/24 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

Ramp Profile
Ave(Iin) at ICOMP
CCM-PFC
ICE3PCS01G
Functional Description
immediately and maintained in off state for the current
PWM cycle. The signal T_OFFMIN resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Gate
Drive
t
Figure 9
Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 4
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of T_OFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
T_OFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D_OFF.
Figure 10 shows the timing diagrams of the T_OFFMIN and
the gate waveforms.
Clock
V ⁽¹⁾
C,ref
Toff_min 600 ns
PWM Cycle
Vram p
GATE
Ramp
Released
t
V (1)
c,ref
is
a
function
of
V ICOMP
Figure 10
Ramp and PWM waveforms
Toff _min
600ns
Peak current limit
Current
limit Latch
RQ
SQ
Current loop
PWM on signal
PWM on
Latch
RQ
SQ
High = turn on Gate
Figure 11
PWM LOGIC
3.8 System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
3.8.1 Input Voltage Brownout Protection(BOP)
Brownout occurs when the input voltage V_IN falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the V_CC has not
entered into the V_CCUVLO level yet. For a system without
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
ICE3PCS01G provides a new BOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network shown in Figure 12. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 9 (BOP) is more than 1.25V. The IC
enters into the fault mode when BOP goes below 1.0V.
The hysteresis prevents the system to oscillate
between normal and fault mode. Note also that the
peak of VIN needs to be at least 20% of the rated V_OUT
in order to overcome OLP and powerup system.
3.7 PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse T_OFFMIN, are
designed to meet a maximum duty cycle D_MAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
Version 2.0
13
5 May 2010