ICE3PCS01G Datasheet, PDF (12/24 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

CCM-PFC
ICE3PCS01G
Functional Description
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
output voltage of integrated PI compensator. This block
has been designed to reduce the voltage loop
dependency on the input voltage in order to support the
wide input voltage range (85VAC-265VAC). Figure 7
gives the relative output power transfer curve versus
the digital word from the integrated PI compensator.
The output power at the input voltage of 85VAC and
maximum digital word of 256 from PI compensator is
set as the normative power and the power curves at
different input voltage present the relative power to the
normative one.
10.00000
power at 85V
power at 265V
1.00000
0.10000
0.01000
LBoost
Rectified
Input Voltage
Rshunt
QB
RGATE
DB
CB
RCS
ISENSE
ICOMP
CICOMP
Current Loop
Current Loop
Compensation
OTA6
5.0mS
+/-50uA (linear range)
S2
5V
Fault
GATE
voltage
proportional to
averaged
Inductor current
PWM
Comparator
C10
Gate
Driver
RQ
S
PWM Logic
Nonlinear
Gain
Input From
Voltage Loop
0.00100
0.00010
0.00001
0
18 37 55 73 91 110 128 146 165 183 201 219 238 256
PI digital output
Figure 7
Power Transfer Curve
3.6 Average Current Control
The choke current is sensed through the voltage
across the shunt resistor and averaged by the ICOMP
pin capacitor so that the IC can control the choke
current to track the instant variation of the input voltage.
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure 8.
It consists of the current loop block which averages the
voltage at ISENSE pin resulted from the inductor
current flowing across R_shunt. The averaged waveform
is compared with an internal ramp in the ramp
generator and PWM block. Once the ramp crosses the
average waveform, the comparator C10 turns on the
driver stage through the PWM logic block. The
Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
Figure 8
Complete System Current Loop
3.6.2 Current Loop Compensation
The compensation of the current loop is implemented
at the ICOMP pin. This is OTA6 output and a capacitor
C_ICOMP has to be installed at this node to ground (see
Figure 8). Under normal mode of the operation, this pin
gives a voltage which is proportional to the averaged
inductor current. This pin is internally shorted to 5V in
the event of standby mode.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous mode (CCM) to achieve the power factor
correction. Assuming the loop voltage is working and
output voltage is kept constant, the off duty cycle D_OFF
for a CCM PFC system is given as:
D_OFF=V_IN/V_OUT
From the above equation, D_OFF is proportional to V_IN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D_OFF, and thus to the input voltage
V_IN. Figure 9 shows the scheme to achieve the
objective.
Version 2.0
12
5 May 2010