ICE3PCS01G Datasheet, PDF (11/24 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

CCM-PFC
ICE3PCS01G
Functional Description
3.5 Voltage Loop
Frequency vs Resistance
260
Resistance Frequency
Resistance
Frequency
240
/kohm
/kHz
/kohm
/kHz
220
15
278
110
40
17
249
120
36
200
20
211
130
34
180
30
141
140
31.5
160
40
106
150
29.5
140
50
86
169
26.2
120
60
74
191
25
70
62
200
23
100
80
55
210
21.2
80
90
49
221
20.2
60
100
43
232
19.2
40
20
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250
Resistance/kohm
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V_OUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from V_OUT. The pin VSENSE is the input of
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
L Boost
DB
Figure 4 Frequency Versus R_FREQ
3.4.2 External Synchronization
The switching frequency can be synchronized to the
external pulse signal after 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Secondly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external R_SYN
combined with R_FREQ and the external diode D_SYN can
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108µs (typical) the switching frequency will be
synchronized to internal clock set by the external
resistor R_FREQ.
Syn. clock
IOSC
1. 0V
QB
Rectified
Input Voltage
RGATE
CB
Current Loop
+
PWM Generation
VIN
Gate Driver
Av(IIN)
Nonlinear
Gain
t
OLP
PI Filter
Notch
Filter
Sigma-
delta
ADC
2.5V
500 ns
C2 a
0.5V
OVP
OVP
QR
QS
C1 a
C1 b
2.5V
2.7V
Figure 6 Voltage Loop
RBVS1
RBVS2
RBVS3
GATE
VSENSE
DSYN
R_SYN
RFREQ
FREQ
OTA 7
2 .5V /1. 25V
C9
SYN
3.5.1 Notch Filter
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output capacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fast output voltage regulation
without influence of the output voltage ripple is
achieved.
Figure 5
Frequency Setting and
Synchronization
3.5.2 Voltage Loop Compensation
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
Version 2.0
11
5 May 2010