SLB9660 Datasheet, PDF (12/22 Pages) Infineon Technologies AG – Trusted Platform Module

SLB 9660 TPM1.2
Trusted Platform Module
Pin Description
4.1
Typical Schematic
Figure 4-3 shows the typical schematic for the SLB 9660. The power supply pins should be bypassed to GND
with capacitors located close to the device. The physical presence input may be connected to a jumper as
shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent).
3.3V
LAD[3:0]
LCLK
LFRAME#
LRESET#
SERIRQ
LAD[3:0]
LCLK
LFRAME#
LRESET#
SERIRQ
VDD
1 µF
GND
4x 100 nF (place close to
device VDD/GND pins)
PP
GPIO
GPIO
NC
Figure 4-3 Typical Schematic
SLB 9660
J1
3.3V
Schematic _SLB9660 .vsd
Data Sheet
12
Revision 1.0 2014-12-12