SLB9665 Datasheet, PDF (11/24 Pages) Infineon Technologies AG – Trusted Platform Module

SLB 9665 TPM2.0
Trusted Platform Module
Pin Description
Table 4-2 I/O Signals (continued)
Pin Number
Name
PG-TSSOP- PG-VQFN-
28-2
32-13
21
22
LCLK
Pin
Type
I
16
18
LRESET# I
6
2
GPIO
I/O
7
31
PP
I
27
28
SERIRQ I/O
Buffer
Type
ST
ST
OD
ST
TS
Function
Clock Input
This pin provides the external clock for the chip
and is typically connected to the PCI clock of the
host. The clock frequency range is 1 MHz - 33 MHz
(nominal).
Reset
External reset signal. Asserting this pin
unconditionally resets the device. The signal is
active low and is typically connected to the
PCIRST# signal of the host.
General Purpose I/O
This pin is a general purpose I/O pin. It is defined
as GPIO-Express-00, please refer to [4] and the
PCI-SIG ECN “Trusted Configuration Space for PCI
Express”.
This pin may be left unconnected; however, to
minimize power consumption, it shall be
connected to a fixed level (either GND or VDD) via
an external resistor (4.7 kΩ..10 kΩ).
Physical Presence
This pin indicates physical presence; for usage of
this signal, please refer to the TCG specification
v1.2. The TPM 2.0 device does not use this
functionality.
For compatibility reasons (downgrade capability
to a TPM 1.2), the pin should be connected to a
jumper. The standard position of the jumper
should connect the pin to GND. If the pin is
connected to VDD, some special commands are
enabled for a TPM 1.2.
This pin does not have an internal pull-up or pull-
down resistor and must not be left floating.
Serial Interrupt Request
Interrupt request signal, uses the serial interrupt
request protocol (see [2]). Connect to the LPC
host.
Data Sheet
11
Revision 1.0 2015-10-27