SLB9665 Datasheet, PDF (10/24 Pages) Infineon Technologies AG – Trusted Platform Module

SLB 9665 TPM2.0
Trusted Platform Module
Pin Description
VDD
GPIO
NC
NC
NC
NC
NC
NC
30
26
1
TPM
22
SLB 9665 VQ 2.0
PG -VQFN - 32- 13
7
18
10
15
LAD1
LFRAME#
LCLK
LAD2
VDD
LAD3
LRESET#
NC
Figure 4-2 Pinout of the SLB 9665VQ2.0 / SLB 9665XQ2.0 (PG-VQFN-32-13 Package, Top View)
Table 4-1 Buffer Types
Buffer Type
Description
TS
Tri-State pin
ST
Schmitt-Trigger pin
OD
Open-Drain pin
Table 4-2 I/O Signals
Pin Number
PG-TSSOP- PG-VQFN-
28-2
32-13
26
27
Name
LAD0
Pin
Type
I/O
23
24
LAD1
I/O
20
21
LAD2
I/O
17
19
LAD3
I/O
22
23
LFRAME# I
Buffer
Type
TS
TS
TS
TS
ST
Function
LPC Address/Data Bit 0
Multiplexed LPC command, address and data bus.
Connect these pins to the LAD[3:0] pins of the LPC
host.
LPC Address/Data Bit 1
see description of LAD0 above.
LPC Address/Data Bit 2
see description of LAD0 above.
LPC Address/Data Bit 3
see description of LAD0 above.
LPC Framing Signal
LPC framing signal. This pin is connected to the
LPC LFRAME# signal and indicates the start of a
new cycle on the LPC bus or the termination of a
broken cycle. The signal is active low.
Data Sheet
10
Revision 1.0 2015-10-27