SSTE32882KB1 Datasheet, PDF (9/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Ball Assignment: MIRROR = HIGH, QCSEN = LOW
This table specifies the pinout for the SSTE32882KB1 in the back configuration (QuadCS mode enabled).
Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and
connecting pad on the module are required in these locations. Blank spaces indicate no ball is populated at that gridpoint, and
vias on the module may be located in these areas.
1
2
3
4
5
6
7
8
9
10
11
A QAA13 QAA8 QCSEN VSS RESET MIRROR ERROUT VSS RSVD QBA8 QBA13
B QAA14 QAA7
QBA7 QBA14
C
QAA9 QAA6
VDD
VDD
VDD
VDD
VDD
QBA6 QBA9
D QAA11 QAA5
VSS
VSS
VSS
VSS
VSS
QBA5 QBA11
E
QAA2 QAA4
VDD
VDD
VDD
VDD
VDD
QBA4 QBA2
F
QAA1 QAA3
VSS
VSS
VSS
VSS
VSS
QBA3 QBA1
G
QAA0 QABA1
VDD
VDD
VDD
VDD
VDD QBBA1 QBA0
H
QAA12 QABA0
VSS
VSS
VSS
VSS
VSS QBBA0 QBA12
J
QABA2 QCS1
VDD
VDD
VDD
VDD
VDD
QCS3 QBBA2
K QAA15 QACKE0 VSS
VSS
VSS
VSS
VSS QBCKE0 QBA15
L
QAWE QCS0
VDD
VDD
VDD
VDD
VDD
QCS2 QBWE
M QAA10 QACKE1 VSS
VSS
VSS
VSS
VSS QBCKE1 QBA10
N QACAS QAODT0 VDD
VDD
VDD
VDD
VDD QBODT0 QBCAS
P QARAS QAODT1 DA4
VSS
VSS
VSS
DA3 QBODT1 QBRAS
R DODT1 DA10
DA1
DA2
DCS3
DA5
DA15 DA14 DCKE1
T DODT0 DCS1
DCS0 DCKE0
U
DCAS DA13
Y1
PVSS
VDD
PVDD
Y0
DBA2 DA12
V
DWE DRAS
Y1
PVSS
VSS
PVDD
Y0
DA11
DA9
W
DBA0
DA0
FBIN
Y3
AVSS
CK
RSVD
Y2 FBOUT DA6
DA8
Y
DBA1 PAR_IN FBIN
Y3
AVDD
CK
VREFCA
Y2 FBOUT DCS2
DA7
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882KB1
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