SSTE32882KB1 Datasheet, PDF (24/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Timing Requirements (DDR3U 1.25V)
COMMERCIAL TEMPERATURE RANGE
Symbol
Parameter
Conditions
DDR3U-800/ DDR3U-1600 Unit
1066/1333
Min Max Min Max
fCLOCK Input Clock Frequency
fTEST Input Clock Frequency
Application Frequency¹
Test Frequency²
300
670 300 810 MHz
70
300
70
300 MHz
tCH/tCL
Pulse Duration, CK, CK
HIGH or LOW
0.4
0.4
tCK3
tACT
Inputs active time before
RESET is taken HIGH⁴
DCKE0/1 = LOW and
DCS[n:0] = HIGH
8
8
tCK3
Command word to
tMRD command word
programming delay
Number of clock cycles
between two command
8
programming accesses
8
tCK3
DCKE[1:0] = LOW;
tINDIS
Input Buffers disable time
after DCKE[1:0] is LOW
RESET = HIGH; CK/CK =
Toggling; RC9[DBA1] = 1
1
and RC9[DBA0] = 0 or 1
4
1
4
tCK3
DCKE[1:0] = LOW;
tQDIS
Output Buffers Hi-Z after
QxCKEn is driven LOW
RESET = HIGH; CK/CK =
Toggling; RC9[DBA1] = 1
1.5
and RC9[DBA0] = 0 or 1
1.5
1.5
1.5
tCK3
Number of tCK required for DCKE[1:0] = LOW;
t_CKOFF
both DCKE0 and DCKE1 RESET = HIGH;
to remain LOW before both CK/CK = Toggling
5
CK/CK are driven low
5
t_CK3
Input buffers (DCKE0 and DCKE[1:0] = LOW;
t_CKEV DCKE1) disable time after RESET = HIGH;
2
CK/CK = LOW
CK/CK = LOW
2
t_CK3
Static Register Output after RC9[DBA1] = 1 and
tFixedout DCKE0 or DCKE1 is
puts HIGH at the input (exit
RC9[DBA0] = 0 or 1
1
from Power Saving state)
tSU Setup Time⁵
Input valid before CK/CK 100
tH
Hold Time⁶
Input to remain valid after
CK/CK
175
3
1
3
tCK3
50
ps
125
ps
1 All specified timing parameters apply.
2 Timing parameters specified for frequency band 2 apply.
3 Clock cycle time.
4 This parameter is not necessarily production tested (see the “Voltage Waveforms for Setup and Hold
Times–Hold Time Calculation” figure below).
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
24
SSTE32882KB1
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