SSTE32882KB1 Datasheet, PDF (13/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Parity, Low Power and Standby with QuadCS Mode Disabled
COMMERCIAL TEMPERATURE RANGE
RESET DCS0
DCS1
Inputs
CK¹
CK¹
 of C/A²
PAR_IN³
Output
ERROUT⁴
H
L
X


Even
L
H
H
L
X


Odd
L
L
H
L
X


Even
H
L
H
L
X


Odd
H
H
H
X
L


Even
L
H
H
X
L


Odd
L
L
H
X
L


Even
H
L
H
X
L


Odd
H
H
H
H
H


X
X
H⁵
H
X
X
L or H
H or L
X
H
X
X
L
L
X
X
ERROUT₀
X
H⁶
L
X or floating X or floating X or floating X or floating X or floating X or floating
H
1 It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels
(LOW and HIGH) when RESET is driven HIGH.
2 C/A= DAn, DBAn, DRAS, DCAS, DWE. Inputs DCKEn, DODTn, and DCSn are not included in this range. This
column represents the sum of the number of C/A signals that are electrically HIGH.
3 PAR_IN arrives one clock cycle after the data to which it applies, ERROUT is issued three clock cycles after the
failing data.
4 This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is low,
it stays latched low for exactly two clock cycles or until RESET is driven low.
5 Same three cycle delay for ERROUT is valid for the de-select phase (see diagram)
6 The system is not allowed to pull CK and CK low while ERROUT is asserted.
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
13
SSTE32882KB1
7326/3