SSTE32882KB1 Datasheet, PDF (73/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Voltage waveforms, CK to ERROUT tHL Measurement
CK
CK
Open Drain Output ERROUT
VTT = VDD/2
VICR
tLH
VID
VOH
VTT
VOL
Voltage waveforms, CK to ERROUT tLH Measurement
CK
VICR
VID
CK
tLH
VOH
Open Drain Output ERROUT
0.65V
0V
Recommended Filtering for the Analog Power Supply (AVDD)
VIA
CARD
R1
VDDQ
1
GND
VIA
CARD
BEAD
4.7uF
0.1uF
2200pF
Place the 2200pF capacitor close to the PLL.
Use a wide trace for the PLL analog power and ground.
Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL).
Bead is 0.8 DC max, 600 at 100MHz.
AVDD
S_SST_SE_TE32_F8₃8₂2₈₈₂
AGND
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
73
SSTE32882KB1
7326/3