SSTE32882KB1 Datasheet, PDF (5/75 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882KB1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Pinout Configuration
Package options include a 176-ball Thin-Profile Fine-Pitch BGA (TFBGA) with 0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm. It
uses the mechanical outline MO-246 variation F. The device pinout supports outputs on the outer two left and right columns to support
easy DIMM signal routing. Corresponding inputs are placed in a way that two devices can be placed back to back for 4 Rank modules
while the data inputs share the same vias. Each input and output is located close to an associated no-ball position or on the outer two
rows to allow low cost via technology combined with the small 0.65mm ball pitch.
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
176-ball Thin Profile Fine Pitch BGA (TFBGA) 11x20 Grid
Top View
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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