ICSSSTUB32864A Datasheet, PDF (9/12 Pages) Integrated Device Technology – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32864A
Advance Information
CK Inputs
TL=50Ω
Test Point
R_L = 100Ω
Test Point
DUT
TL=350ps, 50Ω
CK# _Out
CK
C_L = 30 pF
(see Note 1)
LOAD CIRCUIT
VDD
R_L = 1000Ω
Test Point
R_L = 1000Ω
VCMOS
RST#
Inp ut
t _{in act}
V_DD/2
V_DD/2
V_DD
0V
t_act
CK
V_ICR
CK
V_ID
V_ICR
I_DD
(see
Note 2)
10%
90%
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
t_w
V_ID
t_PLH
t_PHL
Ou t put
V_TT
V_TT
V_OH
V_OL
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
Inpu t
V_ICR
V_ICR
VOLTAGE WAVEFORMS – PULSE DURATION
V_ID
CK
V_ICR
CK
LVCMOS
RST#
In put
V_DD/2
V_IH
V_IL
t_RPHL
t_su
t_h
Inpu t
V_REF
V_IH
V_REF
V_IL
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
Ou t p u t
V_OH
V_TT
V_OL
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
Figure 6 — Parameter Measurement Information (V_DD = 1.8 V ± 0.1 V)
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. t_PLH and t_PHL are the same as t_PDM.
1166—10/05/05
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