ICSSSTUB32864A Datasheet, PDF (8/12 Pages) Integrated Device Technology – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32864A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
MIN MAX
f_clock
t_W
t_ACT
t_INACT
Clock frequency
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
DCS before CK, CK↓,
410
1
10
15
Setup time
CSR high; CSR before
0.6
CK, CK↓, DCS high
t_SU Setup time
DCS before CK, CK↓,
CSR Low
0.5
DODT, DCKE and data
before CK, CK↓
0.5
t_h Hold time
DCS, DODT, DCKE and
data after CK, CK↓
0.4
PAR_IN after CK, CK↓
0.4
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
From
(Input)
To
(Output)
VDD = 1.8V ±0.1V
MIN
TYP MAX
UNITS
fmax
410
MHz
t_PDM1 CLK, CLK#
Q
1.1
t_PDMSS2 CLK, CLK#
Q
t_phl RESET#
Q
Notes: 1. Includes 350ps test-load transmission-line delay
1.5
ns
1.6
3
ns
2. Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
PARAMETER
V_DD = 1.8V ± 0.1V
MIN
MAX
UNIT
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
dV/dt_∆¹
1
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1166—10/05/05
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