ICSSSTUB32864A Datasheet, PDF (10/12 Pages) Integrated Device Technology – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32864A
Advance Information
DUT
Out
V_DD
C_L = 10 pF
(see Note 1)
R_L = 50Ω
Test Point
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Ou t p u t
V_OH
80%
dv _f
20%
dt _f
V_OL
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
C_L = 10 pF
(see Note 1)
Test Point
R_L = 50Ω
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
dv _r
dt _r
80%
V_OH
20%
Ou t put
V_OL
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Figure 7 — Output Slew-Rate Measurement Information (V _DD = 1.8V ± 0.1V)
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, Z_O =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
1166—10/05/05
10