ICSSSTUB32864A Datasheet, PDF (2/12 Pages) Integrated Device Technology – 25-Bit Configurable Registered Buffer for DDR2

ICSSSTUB32864A
Advance Information
Ball Assignments
A ^{DCKE NC}
B ^D2
NC
V _REF
GND
V_DD
GND
QCKEA QCKEB
Q2A
Q2B
C ^D3
NC
D ^{DODT NC}
V_DD
GND
V_DD
GND
Q3A
Q3B
QODTA QODTB
E ^D5
NC
V_DD
V_DD
Q5A
Q5B
F ^D6
NC
GND GND Q6A
Q6B
G ^NC
H ^CK
RST#
DCS#
V_DD
GND
V_DD
GND
C1
C0
QCSA# QCSB#
J ^CK#
CSR# V_DD
V_DD
ZOH
ZOL
K ^D8
NC
GND GND Q8A
Q8B
L ^D9
NC
M ^D10
NC
V_DD
GND
V_DD
GND
Q9A
Q10A
Q9B
Q10B
N ^D11
NC
P ^D12
NC
V_DD
GND
V_DD
GND
Q11A
Q12A
Q11B
Q12B
R ^D13
NC
V_DD
V_DD
Q13A Q13B
T ^D14
NC
V _REF
V_DD
Q14A Q14B
1
2
3
4
5
6
1:2 Register A (C0 = 0, C1 = 1)
Ball Assignments
A D1
B ^D2
C ^D3
D D4
E ^D5
F ^D6
G NC
H ^CK
J ^CK#
K D8
L ^D9
M ^D10
N DODT
P ^D12
R ^D13
T DCKE
1
NC
NC
NC
NC
NC
NC
RST#
DCS#
CSR#
NC
NC
NC
NC
NC
NC
NC
2
V _REF
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
V _REF
3
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
GND
V_DD
V_DD
4
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
C1
C0
QCSA# QCSB#
ZOH ZOL
Q8A
Q8B
Q9A
Q9B
Q10A Q10B
QODTA QODTB
Q12A Q12B
Q13A Q13B
QCKEA QCKEB
5
6
1:2 Register B (C0 = 1, C1 = 1)
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32864A operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the ICSSSTUB32864A must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
1166—10/05/05
2