ICSSSTUAH32868A Datasheet, PDF (9/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
RESET DCS0 DCS1 CLK
Inputs¹
CLK Σ of Inputs = H (D1 - D28)
PAR_IN²
Outputs
QERR³
H
L
X
↑
↓
Even
L
H
H
L
X
↑
↓
Odd
L
L
H
L
X
↑
↓
Even
H
L
H
L
X
↑
↓
Odd
H
H
H
X
L
↑
↓
Even
L
H
H
X
L
↑
↓
Odd
L
L
H
X
L
↑
↓
Even
H
L
H
X
L
↑
↓
H
H
H
↑
↓
H
X
X
↑
↓
L
X or
X or
X or
X or
Floating Floating Floating Floating
Odd
X
X
X or Floating
H
X
X
X or Floating
H
QERR₀₄
QERR₀
H
1 H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2 PAR_IN arrives one clock cycle after the data to which it applies.
3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
4 If DCS0, DCS1, and CSGEN are driven HIGH, the device is placed in low-power mode (LPM). If a parity
error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays
latched LOW for the LPM plus two clock cycles or until RESET is driven LOW.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
9
ICSSSTUAH32868A
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