ICSSSTUAH32868A Datasheet, PDF (17/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
CSGEN
DCS0
DCS1
CLK
COMMERCIAL TEMPERATURE GRADE
tINACT
CLK
Dn, DODTn,
DCKEn
Qn, QODTn,
QCKEn
tRPHL
RESET to Q
PARIN
QERR
tRPLH
RESET to QERR
H, L, or X
H or L
NOTE:
1.After RESET is switched from LOW to HIGH, all data and clock inputs signals must be set and held at valid logic
levels (not floating) for a minimum time of tINACTMAX.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
17
ICSSSTUAH32868A
7115/9