ICSSSTUAH32868A Datasheet, PDF (4/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Block Diagram
M2
RESET
CLK ^L1
CLK ^M1
VREF ^{A5, AB5}
DCKE0, W1, Y1
2
DCKE1
2
DODT0, K1, J1
2
DODT1
2
DCS0
N1
CSGEN ^L2
DCS1
P1
D1 ^A2
COMMERCIAL TEMPERATURE GRADE
D
2
CK Q
R
D
2
CK Q
R
D
CK Q
R
U2, V2 QCKE0A,
QCKE1A
R8, U8 QCKE0B,
QCKE1B
K2, J2 QODT0A,
QODT1A
L7, L8 QODT0B,
QODT1B
N2 _QCS0A
M7 _QCS0B
D
CK Q
R
One of 22 Channels
D ^CE
CK Q
R
P2 _QCS1A
M8 _QCS1B
A7
Q1A
A8
Q1B
TO 21 OTHER CHANNELS
(D2-D12, D17-D20, D22, D24-D28)
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
4
ICSSSTUAH32868A
7115/9