ICSSSTUAH32868A Datasheet, PDF (15/22 Pages) Integrated Device Technology – 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAH32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
CSGEN
DCS0
DCS1
CLK
n
n +1
COMMERCIAL TEMPERATURE GRADE
n+2
n+3
n+4
CLK
Dn, DODTn,
DCKEn
Qn, QODTn,
QCKEn
PARIN
QERR
tACT
tSU
tH
tPDM, tPDMSS
CLK to Q
tSU
tH
tPHL
CLK to QERR
Data to QERR Latency
tPHL, tPLH
CLK to QERR
H, L, or X
H or L
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held LOW for a
minimum time of tACTMAX, to avoid false error.
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and
it will be valid on the n+3 clock pulse.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
15
ICSSSTUAH32868A
7115/9