ICSSSTUAH32865A Datasheet, PDF (9/17 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
DC Electrical Characteristics Over Operating Range
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V.
Symbol Parameter
Test Conditions
VOH Output HIGH Voltage IOH = -12mA, VDDQ = 1.7V
VOL Output LOW Voltage IOL = 12mA, VDDQ = 1.7V
VERROL
PTYERR Output
LOW Voltage
IERROL = 25mA, VDD = 1.7V
IIL All Inputs
VI = VDD or GND; VDD = 1.9V
Static Standby
IO = 0, VDD = 1.9V, RESET = GND
IDD
Static Operating
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = CLK = VIH(AC)
or VIL(AC)
IO = 0, VDD = 1.9V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK = VIH(AC), CLK =
VIL(AC)
Dynamic Operating
(clock only)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle
IDDD
Dynamic Operating
(per each data input)
IO = 0, VDD = 1.8V, RESET = VDD, VI =
VIH(AC) or VIL(AC), CLK and CLK
switching 50% duty cycle. One data input
switching at half clock frequency, 50%
duty cycle.
Dn, PARIN
VI = VREF ± 350mV
CIN CLK and CLK
VICR = 1.25V, VIPP = 360mV
RESET
VI = VDD or GND
Min.
1.2
-5
2
3
Typ.
200
150
500
50
5
Max.
0.5
0.5
Units
V
V
V
+5
μA
μA
10
mA
μA/Clock
MHz
μA/Clock
MHz/
Data
3
4
pF
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
9
IDT74SSTUBH32865A 7103/10