ICSSSTUAH32865A Datasheet, PDF (4/17 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Ball Assignment
Signal Group
Ungated Inputs
Chip Select Gated
Inputs
Chip Select Inputs
Re-Driven
Parity Input
Parity Error
Program Inputs
Clock Inputs
Miscellaneous
Inputs
Signal Name
DCKE0, DCKE1,
DODT0, DODT1
D0 ... D21
DCS0, DCS1
Q0A...Q21A,
Q0B...Q21B,
QCSnA,B
QCKEnA,B,
QODTnA,B
PARIN
PTYERR
CSGateEN
CLK, CLK
MCL, MCH
RESET
VREF
Type
SSTL_18
SSTL_18
SSTL_18
Description
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is
LOW.
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one
will be low when a valid address/command is present.
The register can be programmed to re-drive all
D-inputs only (CSGateEN high) when at least one
Chip Select input is LOW.
SSTL_18
Outputs of the register, valid after the specified clock
count outputs and immediately following a rising edge
of the clock.
SSTL_18
Input parity is received on pin PARIN and should
maintain odd parity across the D0...D21 inputs, at the
rising edge of the clock.
Open Drain
When LOW, this output indicates that a parity error
was output identified associated with the address
and/or command inputs. PTYERR will be active for
two clock cycles, and delayed by an additional clock
cycle for compatibility with final parity out timing on
the industry-standard DDR-II register with parity (in
JEDEC definition).
Chip Select Gate Enable. When HIGH, the D0..D21
inputs will be latched only when at least one Chip
1.8V LVCMOS Select input is LOW during the rising edge of the
clock. When LOW, the D0...D21 inputs will be latched
and redriven on every rising edge of the clock.
SSTL_18
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CLK).
Must be connected to a logic LOW or HIGH.
Asynchronous reset input. When LOW, it causes a
1.8V LVCMOS
reset of the internal latches, thereby forcing the
outputs LOW. RESET also resets the PTYERR
signal.
Input reference voltage for the SSTL_18 inputs. Two
0.9V nominal pins (internally tied together) are used for increased
reliability.
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
4
IDT74SSTUBH32865A 7103/10