ICSSSTUAH32865A Datasheet, PDF (6/17 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
RESET DCS0 DCS1 CLK
Inputs¹
CLK Σ of Inputs = H (D1 - D21)
PARIN²
Outputs
PTYERR³
H
L
X
↑
↓
Even
L
H
H
L
X
↑
↓
Odd
L
L
H
L
X
↑
↓
Even
H
L
H
L
X
↑
↓
Odd
H
H
H
X
L
↑
↓
Even
L
H
H
X
L
↑
↓
Odd
L
L
H
X
L
↑
↓
Even
H
L
H
X
L
↑
↓
Odd
H
H
H
H
H
↑
↓
H
X
X
L or H L or H
L
X or
X or
X or
X or
Floating Floating Floating Floating
X
X
X or Floating
X
X
X or Floating
PTYERR₀
PTYERR₀
H
1 H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
2 PARIN arrives one clock cycle after the data to which it applies.
3 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
6
IDT74SSTUBH32865A 7103/10