ICSSSTUAH32865A Datasheet, PDF (12/17 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

IDT74SSTUBH32865A
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
Parity Logic Diagram
22
22
Dn
D
Q
D
PARIN
D
CLOCK
COMMERCIAL TEMPERATURE GRADE
D
LATCHING AND
RESET FUNCTION
QnA
QnB
PTYERR
Register Timing
CLK
CLK
Dn
PARIN
Qn
n-1
n
tSU tH
n +1
tSU tH
tPDM,
tPDMSS
PTYERR
n+2
n+3
tPDM
n+4
n+5
tPDH
28-BIT 1:2 REGISTERED BUFFER FOR DDR2
12
IDT74SSTUBH32865A 7103/10