ICS952003 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952003
Preliminary Product Review
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_INV
ZCLK_INV
SD_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
0
0
0
0
X
X
X
X
Description
AGP Phase Inversion bit
ZCLK Phase Inversion bit
SDRAM Phase Inversion bit
CPUCLK Phase Inversion bit
PCI clock divider ratio can be
configured via these 4 bits
individually. For divider selection
table refer to table 2. Default at
power up is latched FS divider.
Table 1
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00
/2 /4 /8 /16
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Div (3:2)
00 01 10 11
Div (1:0)
00
/4 /8 /16 /32
01
/3 /6 /12 /24
10
/5 /10 /20 /40
11
/7 /14 /28 /56
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPU_Skew 1
CPU_Skew 0
SD_Skew 1
SD_Skew 0
(Reserved)
PLL2 FS2
PLL2 FS1
PLL2 FS0
PWD
Description
1 ^{These 2 bits delay the CPUCLKT/C (1:0)}
clocks with respect to all other clocks.
1 _{00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps}
0 ^{These 2 bits delay the SDRAM with respect to}
CPUCLK
0 _{00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps}
0 (Reserved)
0
0 (See frequency table below)
0
Frequency Table
B18 bit2 B18 bit1 B18 bit0 VCO
0
0
0
0
0
1 PLL1&2
0
1
0 PLL1&2
0
1
1
PLL2
1
0
0
PLL2
1
0
1
PLL2
1
1
0
PLL2
1
1
1
PLL2
SDRAM ZCLK AGP
Refer to Byte 0, bit 2, 7:4
PLL1 75.40 66.00
PLL1 88.00 75.40
132.00 66.00 66.00
132.00 75.40 66.00
132.00 75.40 75.40
132.00 88.00 75.40
132.00 88.00 88.00
PCI
33.00
37.70
33.00
33.00
37.70
37.70
44.00
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