ICS952003 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952003
Preliminary Product Review
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK
0
0
0
0
0
66.67
66.67 66.67
0
0
0
0
1 100.00 100.00 66.67
0
0
0
1
0 100.00 200.00 66.67
0
0
0
1
1 100.00 133.33 66.67
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0 100.00 160.00 66.67
0
0
1
1
1 100.00 133.33 80.00
0
10
0
0 100.00 200.00 66.67
0
10
0
1 100.00 166.67 62.50
0
10
1
0 100.00 166.67 71.43
0
10
1
1
0
1
1
0
0
0
1
1
0
1 95.00 95.00 63.33
0
1
1
1
0
95.00 126.67 63.33
0
1
1
1
1
1
0
0
0
0 105.00 140.00 70.00
10
0
0
1 100.90 100.90 67.27
1
0
0
1
0 108.00 144.00 72.00
1
0
0
1
1 100.90 134.53 67.27
10
1
0
0 112.00 149.33 74.67
10
1
0
1 133.33 100.00 66.67
10
1
1
0 133.33 133.33 66.67
10
1
1
1 133.33 166.67 66.67
1
1
0
0
0 100.00 133.00 80.00
1
10
0
1 100.00 100.00 80.00
1
1
0
1
0 100.00 166.67 83.33
1
1
0
1
1
1
1
1
0
0 100.00 133.00 100.00
1
1
1
0
1 100.00 100.00 100.00
1
1
1
1
0 100.00 166.67 100.00
1
1
1
1
1
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
AGP
PCI
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
(Reserved)
(Reserved)
66.67
33.33
66.67
33.33
66.67
33.33
62.50
31.25
83.33
41.67
(Reserved)
(Reserved)
63.33
31.67
63.33
31.67
(Reserved)
70.00
35.00
67.27
33.63
72.00
36.00
67.27
33.63
74.67
37.33
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
62.50
31.25
(Reserved)
66.67
33.33
66.67
33.33
62.50
31.25
(Reserved)
PWD
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00000
+/- 0.25% Center Spread _Note1
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
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