ICS952003 Datasheet, PDF (10/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952003
Preliminary Product Review
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
These 4bits control
CPU-ZCLK(1:0)
These 4 bits control
CPU-AGP(1:0)
PWD
Programmable Delay Stop
1 0 0 0 0 1.85ns 1 0 0 0 3.05ns
0 0 0 0 1 2.00ns 1 0 0 1 3.20ns
0 0 0 1 0 2.15ns 1 0 1 0 3.35ns
0 0 0 1 1 2.30ns 1 0 1 1 3.50ns
1 0 1 0 0 2.45ns 1 1 0 0 3.65ns
0 0 1 0 1 2.60ns 1 1 0 1 3.80ns
0 0 1 1 0 2.75ns 1 1 1 0 3.95ns
0 0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 20: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
These 4bits control
CPU-PCICLK_F(1:0)
These 4 bits control
CPU-PCICLK(5:0)
PWD
Programmable Delay Stop
0 0 0 0 0 1.85ns 1 0 0 0 3.05ns
1 0 0 0 1 2.00ns 1 0 0 1 3.20ns
0 0 0 1 0 2.15ns 1 0 1 0 3.35ns
0 0 0 1 1 2.30ns 1 0 1 1 3.50ns
0 0 1 0 0 2.45ns 1 1 0 0 3.65ns
1 0 1 0 1 2.60ns 1 1 0 1 3.80ns
0 0 1 1 0 2.75ns 1 1 1 0 3.95ns
0 0 1 1 1 2.90ns 1 1 1 1 4.10ns
Byte 21: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
24/48_Slew
AGP_Slew
ZCLK_Slew
REF_Slew
PWD
Description
0 _{24/48 MHz clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal; 10 = weak}
0 _{AGP clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal; 10 = weak}
0 _{ZCLK clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal; 10 = weak}
0 _{REF clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal; 10 = weak}
Byte 22: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SDRAM Slew
(Reserved)
PCICLK_F Slew
PCICLK Slew
PWD
Description
0 _{SDRAM clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal;10 = weak}
X
X
(Reserved)
0 _{PCICLK_F clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal;10 = weak}
0 _{PCICLK clock slew rate control bits.}
0 ^{01 = strong; 00, 11 = normal;10 = weak}
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