ICS952003 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4™ processor

Integrated
Circuit
Systems, Inc.
ICS952003
Preliminary Product Review
Byte 5: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin#
30
31
PWD
1
1
Bit 5 26
0
Bit 4 15
X
Bit 3 14
X
Bit 2
4
X
Bit 1
3
X
Bit 0
2
X
Description
AGPCLK1
AGPCLK1
SEL24_48MHz
(0=24MHz, 1=48MHz)
FS4 Read Back
FS3 Read Back
FS2 Read Back
FS1 Read Back
FS0 Read Back
Byte 6: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
10
9
14
15
40, 39
44, 43
39, 40
43, 44
PWD
1
1
0
0
1
1
1
1
Description
ZCLK1
ZCLK0
PCICLK_F0 stop control
0 = Free Running; 1 = Stop
PCICLK_F1 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C0 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C1 stop control
0 = Free Running; 1 = Stop
CPUCLKT/C0 output control
CPUCLKT/C1 output control
Byte 7: Output Control Register
(1 = enable, 0 = disable)
Bit Pin# PWD
Bit 7 15
1 PCICLK_F1
Bit 6 14
1 PCICLK_F0
Bit 5 23
1 PCICLK5
Bit 4 22
1 PCICLK4
Bit 3 21
1 PCICLK3
Bit 2 20
1 PCICLK2
Bit 1 17
1 PCICLK1
Bit 0 16
1 PCICLK0
Description
Byte 8: Byte Count Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0 _{Note: Writing to this register will configure}
0 _{byte count and how many bytes will be}
1 ^{read back, default is 0F}_H ^{= 15 bytes.}
1
1
1
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