ICS853S310I Datasheet, PDF (9/17 Pages) Integrated Device Technology – Two selectable differential input pairs

ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 3A to 3F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
R6
100Ω - 200Ω 100Ω - 200Ω
3.3V
C1
PCLK
C2
VBB
nPCLK
LVPECL
R1
R2
50Ω 50Ω
Input
Figure 3C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
120Ω
R4
120Ω
3.3V
PCLK
R1
120Ω
R2
120Ω
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1
R2
1k
1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 3E. PCLK/nPCLK Input Driven by an SSTL Driver
Figure 3F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
ICS853S310CVI REVISION A NOVEMBER 17, 2010
9
©2010 Integrated Device Technology, Inc.