ICS853S310I Datasheet, PDF (11/17 Pages) Integrated Device Technology – Two selectable differential input pairs

ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Schematic Example
Figure 5A shows a schematic example of the ICS853S310I. In this
example, the PCLK0, nPCLK0 input is selected. The decoupling
capacitors should be physically located near the power pin. For
ICS853S310I, the unused outputs can be left floating.
VCC
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL Driv er
R9
50
C5 (Option)
0.1u
U1
VCC
26
27
28
1
2
3
4
VEE
CLK_SEL
PCLK0
VCC
nPCLK0
VBB
PCLK1
R10
R3
50
1K
ICS853310
R11
50
(U1-8)
VCC
C1
0.1uF
VCC=3.3V
(U1-15) (U1-22) (U1-1)
C2
0.1uF
C3
0.1uF
C4
0.1uF
3.3V
Q3
nQ3
Q4
VCCO
nQ4
Q5
nQ5
18
17
16
15
14
13
12
Zo = 50
Zo = 50
+
-
R2
R1
50
50
C6 (Option)
R3
0.1u
50
Zo = 50
Zo = 50
+
-
R8
R7
50
50
C7 (Option)
R13
0.1u
50
Figure 5A. ICS853S310I LVPECL Clock Output Buffer Schematic Example
ICS853S310CVI REVISION A NOVEMBER 17, 2010
11
©2010 Integrated Device Technology, Inc.