ICS853S310I Datasheet, PDF (12/17 Pages) Integrated Device Technology – Two selectable differential input pairs

ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Power, Ground and Bypass Capacitor
This section provides a layout guide related to power, ground and
placement of bypass capacitors for a high-speed digital IC. This
layout guide is a general recommendation. The actual board design
will depend on the component types being used, the board density
and cost constraints. This description assumes that the board has
clean power and ground planes. The goal is to minimize the ESR
between the clean power/ground plane and the IC power/ground pin.
A low ESR bypass capacitor should be used on each power pin. The
value of bypass capacitors ranges from 0.01uF to 0.1uF. The bypass
capacitors should be located as close to the power pin as possible. It
is preferable to locate the bypass capacitor on the same side as the
IC. Figure 5B shows suggested capacitor placement. Placing the
bypass capacitor on the same side as the IC allows the capacitor to
have direct contact with the IC power pin. This can avoid any vias
between the bypass capacitor and the IC power pins.
The vias should be placed at the Power/Ground pads. There should
be a minimum of one via per pin. Increasing the number of vias from
the Power/Ground pads to Power/Ground planes can improve the
conductivity.
GND
IC
Power Pad
Power pin
GND Pin
GND Pad
Via
Figure 5B. Recommended Layout of Bypass Capacitor Placement
ICS853S310CVI REVISION A NOVEMBER 17, 2010
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