ICS853S310I Datasheet, PDF (2/17 Pages) Integrated Device Technology – Two selectable differential input pairs

ICS853S310I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
27
28
Name
V_CC
nPCLK0
V_BB
PCLK1
nPCLK1
nc
nQ7, Q7
V_CCO
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
V_EE
CLK_SEL
PCLK0
Type
Power
Input
Pullup/
Pulldown
Output
Input
Input
Unused
Pulldown
Pullup/
Pulldown
Output
Power
Output
Output
Output
Output
Output
Output
Output
Power
Input
Pulldown
Input
Pulldown
Description
Positive supply pin.
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Bias voltage to be connected for single-ended applications.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
No connect
Differential output pair. LVPECL/ECL interface levels.
Output supply pins.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW,
selects PCLK0, nPCLK0 inputs. LVPECL single-ended interface levels. Also
accepts standard LVCMOS input levels.
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
R_PULLDOWN Input Pulldown Resistor
R_VCC/2
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
kΩ
kΩ
ICS853S310CVI REVISION A NOVEMBER 17, 2010
2
©2010 Integrated Device Technology, Inc.