ICS853S310I Datasheet, PDF (1/17 Pages) Integrated Device Technology – Two selectable differential input pairs

Low Skew, 1-to-8 Differential-to-
3.3V LVPECL/ECL Fanout Buffer
ICS853S310I
DATA SHEET
General Description
The ICS853S310I is a low skew, high performance 1-to-8
Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx,
nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL
differential input levels. The ICS853S310I is characterized to operate
from a 3.3V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853S310I ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Features
• Eight differential 3.3V LVPECL/ECL outputs
• Two selectable differential input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2GHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLKx input
• Output skew: 20ps (typical)
• Propagation delay: 825ps (typical)
• Additive phase jitter, RMS: 0.14ps (typical)
• LVPECL mode operating voltage supply range:
V_CC = 3.0V to 3.8V, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.0V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available lead-free (RoHS 6) package
Block Diagram
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
0
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
1
CLK_SEL ^Pulldown
V_BB
Pin Assignment
Q0
nQ0
25 24 23 22 21 20 19
Q1
VEE 26
18 Q3
nQ1
CLK_SEL 27
17 nQ3
Q2
PCLK0 28
16 Q4
nQ2
VCC 1
15 ^VCCO
Q3
nPCLK0 2
14 nQ4
nQ3
VBB 3
13 Q5
PCLK1 4
Q4
12 nQ5
5 6 7 8 9 10 11
nQ4
Q5
nQ5
ICS853S310I
Q6
nQ6
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
Q7
V Package
nQ7
Top View
ICS853S310CVI REVISION A NOVEMBER 17, 2010
1
©2010 Integrated Device Technology, Inc.