ICS853S01I Datasheet, PDF (9/23 Pages) Integrated Device Technology – One LVPECL output pair

ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1A shows how a differential input can be wired to accept single
ended levels. The reference voltage V_REF = V_CC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V_REF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and V_CC = 3.3V,
R1 and R2 value should be adjusted to set V_REF at 1.25V. The values
below are for when both the single ended swing and V_CC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V_IL cannot be less
than -0.3V and V_IH cannot be more than V_CC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1A. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Wiring the Differential Input to Accept
Single-ended LVPECL Levels
Figure 1B shows an example of the differential input that can be wired
to accept single-ended LVPECL levels. The reference voltage level
V_BB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the input
pin.
C1
0.1uF
CLK_IN
VCC
PCLK
VBB
nPCLK
ICS853S01AGI REVISION A OCTOBER 29, 2012
Figure 1B. Single-Ended LVPECL Signal Driving
Differential Input
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©2012 Integrated Device Technology, Inc.