ICS853S01I Datasheet, PDF (16/23 Pages) Integrated Device Technology – One LVPECL output pair

ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S01I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S01I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 26mA = 90.09mW
• Power (outputs)_MAX = 32mW/Loaded Output pair
Total Power__MAX (3.3V, with all outputs switching) = 90.09mW + 32mW = 122.09mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 100°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.122W * 100°C/W = 97.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance _JA for 16 Lead TSSOP, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
100.0°C/W
1
94.2°C/W
2.5
90.2°C/W
Table 6B. Thermal Resistance _JA for 16 Lead VFQFN, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
1
65.3°C/W
2.5
58.5°C/W
ICS853S01AGI REVISION A OCTOBER 29, 2012
16
©2012 Integrated Device Technology, Inc.