ICS853S01I Datasheet, PDF (1/23 Pages) Integrated Device Technology – One LVPECL output pair

2:1 Differential-to-LVPECL Multiplexer
ICS853S01I
DATA SHEET
General Description
The ICS853S01I is a high performance 2:1 Differential-to-LVPECL
Multiplexer. The ICS853S01I can also perform differential translation
because the differential inputs accept LVPECL, LVDS and CML
levels. The ICS853S01I is packaged in a small 3mm x 3mm 16
VFQFN package, making it ideal for use on space constrained
boards.
Features
• One LVPECL output pair
• Two selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML
• Translates LVCMOS/LVTTL input signals to LVPECL levels by
using a resistor bias network on nPCLKx, nPCLKx
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 490ps (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
Block Diagram
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
0
Q
PCLK1 ^Pulldown
nQ
nPCLK1 ^{Pullup/Pulldown}
1
CLK_SEL ^Pulldown
V_BB
Pin Assignments
16 15 14 13
PCLK0 1
12 VEE
nPCLK0 2
11 Q
PCLK1 3
10 nQ
nPCLK1 4
9 VEE
5 6 78
ICS853S01I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
PCLK0 1
nPCLK0 2
PCLK1 3
nPCLK1 4
VBB 5
CLK_SEL 6
nc 7
VCC 8
16 nc
15 VEE
14 VEE
13 VCC
12 VEE
11 Q
10 nQ
9 VEE
ICS853S01I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
ICS853S01AGI REVISION A OCTOBER 29, 2012
1
©2012 Integrated Device Technology, Inc.