ICS853S01I Datasheet, PDF (2/23 Pages) Integrated Device Technology – One LVPECL output pair

ICS853S01I Data Sheet
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7, 16
8, 13
9, 12, 14, 15
10, 11
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V_BB
CLK_SEL
nc
V_CC
V_EE
nQ, Q
Type
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Output
Input
Pulldown
Unused
Power
Power
Output
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Bias voltage.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When
LOW, selects PCLK0, nPCLK0 inputs. LVCMOS/LVTTL interface levels.
No connect.
Positive supply pins.
Negative supply pins.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
R_PULLDOWN
R_PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
37
Maximum
Units
pF
k
k
Function Tables
Table 3. Control Input Function Table
CLK_SEL
Input Selected
0
PCLK0, nPCLK0
1
PCLK1, nPCLK1
ICS853S01AGI REVISION A OCTOBER 29, 2012
2
©2012 Integrated Device Technology, Inc.