ICS810251 Datasheet, PDF (9/15 Pages) Integrated Device Technology – VCXO and Synchronous Ethernet Jitter Attenuator

ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Schematic Example
Figure 1 shows an example of the 810251I application schematic. In
this example, the device is operated either at V_DD = 3.3V or 2.5V. The
decoupling capacitors should be located as close as possible to the
power pin. The input is driven by an LVCMOS driver. An optional
3-pole filter can also be used for additional spur reduction. It is
recommended that the loop filter components be laid out for the
3-pole option. This will also allow the 2-pole filter to be used.
3-pole loop filter example - (optional)
R3
LF0
LF1
Rs
TBD
TBD
Cp
C3
Cs
TBD
TBD
TBD
C5
SPARE X2
C6
SPARE
XTAL_OUT
XTAL_IN
Rs
1K
Cp
Cs
0.001 uF
10uF
2-pole loop filter
Q1
R1 ₃₃
Zo = 50
LVCMOS_Driv er
VDD
C1
0.1u
VDD
9
10
11
12
13
14
15
16
GND
XTAL_OUT
XTAL_IN
GND
LF0
LF1
VDD
CLK_IN
VDD
VDDA
OE
VDDO
Q
Reserv ed
GND
PLL_SEL
8
7
6
5
4
3
2
1
VDDO
C2
0.1u
VDDA
C30
0.01u
R2
VDD
10
C45
10u
C4 U1
0.1u
R4 33
Zo = 50
Logic Control Input Examples
LVCMOS_Receiv er
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD=VDDO=3.3V
Figure 1. P.C. ICS810251I Schematic Example
ICS810251AGI REVISION B OCTOBER 5, 2012
9
©2012 Integrated Device Technology, Inc.