ICS810251 Datasheet, PDF (2/15 Pages) Integrated Device Technology – VCXO and Synchronous Ethernet Jitter Attenuator

ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1
2, 9, 12
3
4
5
6
7
8, 15
10,
11
13, 14
16
Name
PLL_SEL
GND
Reserved
Q
V_DDO
OE
V_DDA
V_DD
XTAL_OUT,
XTAL_IN
LF0, LF1
CLK_IN
Type
Input
Pullup
Power
Reserved
Output
Power
Input
Power
Power
Pullup
Input
Analog
Input/
Output
Input
Pulldown
Description
When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in
bypass mode. LVCMOS/LVTTL interface levels.
Power supply ground.
Reserved pin. Do not connect.
Single-ended clock output. LVCMOS/ LVTTL interface levels.
Output power supply pin.
Output enable pin for Q output. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Loop filter connection node pins.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
Parameter
Input Capacitance
C_PD
Power Dissipation Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
R_OUT
Output Impedance
Test Conditions
V_DD, V_DDO = 3.465V
V_DD, V_DDO = 2.625V
V_DDO = 3.3V±5%
V_DDO = 2.5V±5%
Minimum
Typical
4
8
5
51
51
15
20
Maximum
Units
pF
pF
pF
k
k


ICS810251AGI REVISION B OCTOBER 5, 2012
2
©2012 Integrated Device Technology, Inc.