 English |
|
|
|
|
|
|
|
| ICS810251 Datasheet, PDF (4/15 Pages) Integrated Device Technology – VCXO and Synchronous Ethernet Jitter Attenuator | |||
| |||
| ◁ |
ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VIH
Input
High Voltage
VIL
Input
Low Voltage
IIH
Input
High Current
CLK_IN
OE, PLL_SEL
IIL
Input
Low Current
CLK_IN
OE, PLL_SEL
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VDD = 3.465V
VDD = 2.625V
VDD = 3.465V
VDD = 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
VDD = 3.465V or 2.625V, VIN = 0V
VDDO = 3.3V ± 5%
VDDO = 2.5V ± 5%
VDDO = 3.3V ± 5%
VDDO = 2.5V ± 5%
2
1.7
-0.3
-0.3
-5
-150
2.6
1.8
VDD + 0.3
VDD + 0.3
0.8
0.7
150
5
0.6
0.5
NOTE 1: Outputs terminated with 50ï to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF
Input Reference Frequency
fVCO
fOUT
tJIT(CC)
tjit(ï±)
VCXO-PLL Frequency
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2
fOUT = 25MHz, Integration Range:
1kHz â 1MHz
tJIT(PER) Period jitter
tR / tF
Output Rise/Fall Time
20% to 80%
500
odc
Output Duty Cycle; NOTE 3
48
odc
Output Duty Cycle; NOTE 4
45
Typical
25
125
25
25
0.22
Maximum
45
5
1200
52
55
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 616Hz bandwidth filter.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: Specified with the VCXO-PLL free running high.
NOTE 4: Specified with the VCXO-PLL locked.
ICS810251AGI REVISION B OCTOBER 5, 2012
4
©2012 Integrated Device Technology, Inc.
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese