ICS810251 Datasheet, PDF (7/15 Pages) Integrated Device Technology – VCXO and Synchronous Ethernet Jitter Attenuator

ICS810251I Data Sheet
Parameter Measurement Information
1.65V±5
1.65V±5
V_DD,
V_DDO
V_DDA
GND
SCOPE
Qx
-1.65V±5
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
1.25V±5
1.25V±5
V_DD,
V_DDO
V_DDA
GND
SCOPE
Qx
-1.25V±5
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
V
DDO
Q
2
V
DDO
2
V
DDO
2
tcycle n
➤
tcycle n+1
➤
| | tjit(cc) = ^{tcycle n – tcycle n+1}
1000 Cycles
Cycle-to-Cycle Jitter
Phase Noise Plot
Phase Noise Mask
f₁ ^{Offset Frequency} f₂
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
V_OH
V_REF
1σ contains 68.26% of all measurements
V_OL
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10^-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Period Jitter
20%
Q
80%
t_R
Output Rise/Fall Time
80%
t_F
20%
ICS810251AGI REVISION B OCTOBER 5, 2012
7
©2012 Integrated Device Technology, Inc.