ICS527R-01ILF Datasheet, PDF (9/11 Pages) Integrated Device Technology – CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER

ICS527-01
CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER
ZDB AND MULTIPLIER/DIVIDER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
F_IN
0.6
0 to +70° C
4
Output Frequency, CLK1
F_{OUT -40 to +85° C}
4
CLK1 Frequency for Correct
SYNC Operation
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Power Down Time, PDTS low to
clocks tri-stated
t_OR 0.8 to 2.0 V
t_OF 2.0 to 0.8 V
t_OD
Measured at VDD/2,
C_L=15 pF
1
1
45
50
Power Up Time, PDTS high to
clocks stable
Absolute Clock Period Jitter
One sigma Clock Period Jitter
Skew of Output Clocks
Input Capacitance
Input to Output Skew
Device to Device Skew
t_ja Deviation from mean
± 90
t_js
40
t_IO CLK1 to CLK2, Note 1 -250
C_IN
4
t_IO ICLK to FBIN, Note 1
-250
t_pi Common ICLK, at FBIN
0
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Max.
200
160
140
66
55
50
10
250
250
500
Units
MHz
MHz
MHz
MHz
ns
ns
%
ns
ms
ps
ps
ps
pF
ps
ps
External Components
The ICS527-01 requires two 0.01 µF decoupling capacitors to be connected between VDD and GND, one
on each side of the chip. They must be connected close to the device to minimize lead inductance. No
external power supply filtering is required for this device. A 33Ω series terminating resistor should be used
on the CLK1 and CLK2 output pins.
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 9
ICS527-01 REV G 051310